The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). The ICs are usually formed using both P-channel and N-channel FETs in which case the IC is referred to as a complementary MOS or CMOS integrated circuit (IC). There is a continuing trend to incorporate more circuitry having greater complexity on a single IC chip. To continue this trend, the size of each individual device in the circuit and the spacing between device elements, or the pitch, is reduced for each new technology generation.
As critical dimensions shrink, device components such as the gate length and the thickness of gate insulator layers are scaled down in substantial proportion with each technology node. At the 65 nm node, conventional gate insulator materials such as, for example, thermally grown silicon dioxide (SiO2) or deposited silicon oxynitride (SiON), begin to exhibit excessive leakage current and thus provide only marginally sufficient electrical isolation between the gate electrode and the underlying channel of a transistor. The problem of excessive leakage current is compounded when metal gate electrodes are used because such electrodes can reduce the oxide, thereby further decreasing its insulating properties. Therefore, alternative materials having dielectric constants greater than about 7 (referred to herein as high-k dielectrics) have been considered for use with advanced devices including advanced CMOS devices. Gate insulators made from high-k dielectrics can be made thicker than those made with SiO2 without sacrificing capacitance, and thus offer the benefit of a significant reduction in leakage current. Candidate materials include transitional metal oxides, silicates, and oxynitrides such as hafnium oxide, hafnium silicate, and hafnium oxynitride.
However, many high-k dielectrics, while offering improved insulating properties, also retain certain negative characteristics that can potentially degrade device performance. For example, high-k dielectrics typically contain metal-oxygen bonds that are polarizable. As a result, when placed under an electric field (such as that applied to a gate electrode), these materials generate remote phonons that can cause charge scattering. Such scattering reduces the mobility of charge carriers in the channel, reducing transistor drive current thereby. In addition, charge trapping at the interface between the channel and the high-k insulator or within the high-k dielectric itself can alter the threshold voltage (Vt) of a transistor, rendering its performance inconsistent. Further, such trapped charges can lead to excessive coulomb scattering of channel carriers that can further reduce drive current. These undesirable effects are exacerbated when a high-k gate dielectric is positioned in close proximity to a channel, which often is the case in advanced devices fabricated for the 45 nm technology node and beyond.
Accordingly, it is desirable to provide semiconductor devices having gate channels that are buried by a capping layer interposed between a channel and a high-k gate dielectric. Further it is also desirable to provide methods for fabricating such semiconductor devices. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.